As integrated circuits increase in size and complexity, test compression is becoming a requirement for reducing test data volume and test application time. Test compression compresses the amount of both stimuli and response data that must be stored in a tester or automatic test equipment (ATE).
Test stimulus compression is done by adding a decompressor at the scan input side of the scan chains for decompressing n-input compressed test patterns stored in the tester to m-input decompressed test patterns for driving m internal scan chains during each scan shift cycle, where n<m. The decompressor can be a linear feedback shift register (LFSR) based finite-state machine or a combinational logic network using a multiplexer (MUX) network or exclusive-OR (XOR) network. When a combinational logic network is used, the decompressor is also referred to as a broadcaster.
Test response compaction is done by adding a compactor at the scan output side of the scan chains for compacting the test response. If the test response is deterministic and contains all known values, a simple approach of using a multiple-input signature register (MISR) can be used to compress the entire output response down to a single final signature. However, in many cases the output response may contain a number of unknown (X) values that cannot be predicted ahead of time. There are many sources of X's, for example uninitialized memory, bus contention, non-scan latches and flip-flops, floating tri-states, multi-cycle paths, cross-clock-domain logic, etc. These X values corrupt the final signature in a MISR making it unpredictable and hence unusable. This is a major issue for test compression and BIST. A number of schemes have been developed to deal with the problem of X's in the output response.
One approach is to modify the circuit-under-test (CUT) in the design phase to eliminate the sources of X values so that the output response contains only known values. This is often called X-bounding or X-blocking. It involves inserting design-for-testability (DFT) hardware into the CUT to prevent X's from propagating to scan cells. However, some X's, e.g., those due to races, may become known very late in the design or manufacturing stage, and thus cannot be eliminated. Also, in some cases, it is not desirable to modify the design, e.g., when using legacy designs, macrocells, hard cores, etc.
Another approach, which does not require modifying the CUT, is to use X-masking. This involves masking out the X's at the input to the compactor. Mask data is required to specify which scan chain outputs should be masked in each clock cycle. A number of techniques have been developed for designing the masking hardware and compressing the amount of mask data that is required including Barnhart et al. (2001), Wohl et al. (2001, 2003, 2004), Pomeranz et al. (2002), Chickermane et al. (2004), Volkerink et al. (2005), Chao et al. (2005), Tang et al. (2006), Rajski et al. (2006), and Wang et al. (2007). In most cases, the resolution of the masking is reduced in order to keep the amount of mask data at reasonable levels (e.g., an entire scan chain may be masked or an entire scan slice may be masked). This results in some non-X values also getting masked which reduces observability and may impact the coverage, particularly for unmodeled faults.
A third approach is to use an X-tolerant compactor that can compact an output stream that contains X's. This is an attractive approach as it eliminates the need for X-masking. In U.S. Pat. No. 7,185,253 and also published in Mitra et al. (2004), an X-tolerant compactor, called X-Compact, is described which consists of a combinational circuit that compacts n scan chains outputs in each clock cycle down to m bits which are compared with the expected response on the tester. It is illustrated in FIG. 1. When X's arrive at the input of the compactor, they propagate to some of the m output bits thereby corrupting them. The corrupted output bits are masked (i.e., ignored) by the tester. The key idea in X-Compact is to design the combinational circuit so that in the presence of a limited number of X inputs, enough of the compacted outputs are left uncorrupted such that errors on the non-X inputs can still be detected. The compaction ratio of n to m depends on the number of X's that are guaranteed to be tolerated. To maximize the compaction ratio, typically only one X would be guaranteed to be tolerated per clock cycle.
In U.S. patent application Ser. No. 10/778,950 (2004) and also published in Rajski et al. (2005), an X-tolerant compactor, called a convolutional compactor, is described. It uses a combinational compactor whose outputs are XORed into different stages of multiple shift registers. It is illustrated in FIG. 2. Each compacted output bit is thus a function of scan chain outputs across a window of consecutive clock cycles. A convolutional compactor allows tradeoffs in terms of the compaction ratio versus the number of X's that can be tolerated across a window of clock cycles.
Mitra et al. (2004) at the IEEE International Test Conference describes an X-tolerant multiple-input signature register (MISR) approach that is based on stochastic coding. It is illustrated in FIG. 3. Based on the probability of X's in the output stream, a weighted linear combination of scan chain outputs is fed to each MISR input. The weight logic is designed so as to minimize the expected number of bits in the MISR that get corrupted by X's. The corrupted bits in the MISR are masked on the tester while the non-corrupted bits are compared with the fault-free signature. The error coverage is probabilistic and will vary depending on the distribution of X's in the output stream. Error coverage can be improved by using more intermediate signatures or running the test multiple times with different linear combinations. The overhead scales with the product of the MISR size and number of scan chains and can be reduced by using multiple local MISRs. The main drawback of this approach is the need for a large number of intermediate MISR signatures and/or large area overhead in order to achieve high error coverage.
An object of the present invention is to provide an improved and more efficient X-tolerant scheme for compacting output streams using a Misr.